1. Field of the Invention
The present invention relates to a scanning circuit, a solid-state image sensor, and a camera.
2. Description of the Related Art
A solid-state image sensor can include a scanning circuit including a shift register to read out the pixel signal of each pixel in a pixel array. The scanning circuit is provided with a plurality of signal lines. The shift register can be driven by a plurality of first signal lines to transmit in-phase signals and a plurality of second signal lines to transmit opposite-phase signals. Such an arrangement including a plurality of signal lines needs to be designed in consideration of the capacitive coupling or crosstalk between the signal lines.
Japanese Patent Laid-Open No. 2-284449 discloses a wiring pattern of a bus line semiconductor memory device in which the distance between a plurality of first signal lines and a plurality of second signal lines is larger than that between the plurality of first signal lines (or between the second signal lines). According to this structure, capacitive coupling is suppressed between the signal lines that transmit in-phase signals, and crosstalk is suppressed between the signal lines that transmit opposite-phase signals. Hence, the above-described structure can effectively be applied to the wiring pattern of signal lines of a scanning circuit.
However, since this reduces the time difference in the timing to drive buffers provided on the respective signal lines, a voltage drop may occur due to an increase in the total amount of instantaneously generated through currents. This can be a more serious problem as the number of buffers increases.